"wait ARMv9??"
"uh. wrong one. there are two
without the v. ARM9"
"oh uh so it's ARMv4"
"yea- oh no it's. ARM9**E. it's ar-"
"i will destroy britain"

@qdoit ARM926EJ is uhhh ARMv5TE right

@qdoit it's ARMv5TEJ apparently

but nobody cares about Jazelle anyways

@whitequark @qdoit ARMv5TEJ (assuming you mean ARM926EJ, I don't think ARM926J exists)

@noisytoot @qdoit yes and yes (see the edit)

@whitequark @qdoit

~ # cat /proc/cpuinfo 
Processor       : ARM926EJ-S rev 5 (v5l)
BogoMIPS        : 191.69
Features        : swp half thumb fastmult edsp java 
CPU implementer : 0x41
CPU architecture: 5TEJ
CPU variant     : 0x0
CPU part        : 0x926
CPU revision    : 5

Hardware        : ASPEED-AST2300
Revision        : 0000
Serial          : 0000000000000000

@whitequark @qdoit (hi, i'm nobody;)

@jn @qdoit tell me more!

@whitequark @qdoit i made a writeup a while ago as my entry to BGGP5, the @binarygolf grand prix. Jazelle hardware is extremely common in that era of embedded systems, but licensed software (i presume it had to be licensed from arm) is practically non-existent. the Hackspire (TI nSpire homebrew) people documented how to enter Jazelle mode and how ARM registers map to the Java value stack, i built a sort-of-FORTH on top.

https://codeberg.org/neuschaefer/bggp5-jazelle

@qdoit not to be confused with an ARM Cortex-A9 or an Apple A9, of course

@jn @whitequark @qdoit @binarygolf this is amazing lol

@jn @whitequark @qdoit @binarygolf it always makes me sad when I see an ARM7/9 without Jazelle

@jn @qdoit @binarygolf siiiick

@jn @whitequark @qdoit @binarygolf this is fun!

@qdoit Ah, shades of IMAP4rev1 - both of them.